The invention generally relates to a manufacturing process for producing circuit board substrates, and more particularly to the process of patterning, metallizing, and layering dielectric materials according to a desired number of layers.
Multi-layered printed circuit board substrates are well known. These substrates utilize plural stacked circuit boards with additional layers of dielectric materials that separate conductors. The multi-layer substrates usually incorporate interconnections extending between the conductors on the various layers in the stack, in order to provide the necessary electrical interconnections. Electrical interconnections between conductors in the various layers of multi-layered PCBs are accomplished through vias.
The production of these multi-layered substrates usually involves the use of catalysts to assist with interlayer formation. Known methods of production utilize bulk dielectric materials, which include catalysts dispersed therein. A problem with the inclusion of the catalyst in the dielectric is that the quality of the dielectric is compromised. This makes the resulting substrate less desirable for high frequency applications because of magnetic interference and other disturbances. In other words, the inclusion of the catalyst in the dielectric is detrimental to the electrical performance. Furthermore, the process is expensive.
One known method that includes a dispersion of catalyst in the bulk dielectric is the additive process. This process involves, first, providing the raw material, usually a casting or extrusion of dielectrics or impregnation of fiber reinforcement with dielectric resins that contain a catalyst. Second, patterning of the internal conductors. This involves the application of permanent photosensitive resist, then exposure to actinic light followed by the development of the resist, and then electroless deposition of a metal. Third is a multi-layering process. Several patterned internal layers are stacked. These layers are interleaved with an adhesive. The layers are pressure and heat laminated. Fourth, a via is formed between the layers. This is accomplished by drilling, punching, or ablating the dielectric to form the via followed by electroless deposition of a metal. Fifth, the exterior conductors are patterned.
A problem with this process is that the conductors are formed using photosensitive resist. Also, as stated above, the bulk of the dielectric contains a dispersion of a catalyst and this makes the substrate electrically inferior to similar non-catalyzed resins. This process is also more expensive than processes using non-catalyzed resins.
A recent method of manufacturing a multi-layered substrate that avoids these problems is outlined in EP 677,985 A1. This process includes: First, providing a casting or extrusion of any un-reinforced dielectric that is suitable for ablation to form internal layers. This dielectric is called a raw sheet. Second, a multi step laser ablation of the dielectric follows in order to form conductor and pad cavities on both sides of the dielectric. This step is followed by more laser ablation to form the vias. The third step is the metallization of the internal layers. This is achieved by sputtering a thin layer of metal on the entire surface of the dielectric substrate followed by the deposit of an additional metal layer to achieve the desired thickness in the cavities. Fourth, excess metal is then removed from outside the conductor pattern area by a grinding or polishing process. Fifth, the next step is a multi-layering process. Another raw sheet is laminated over the patterned internal layer with heat and pressure followed by steps 2 through 4 until all layers have been processed.
While the method of EP 677,985 A1 is an important advance, it has several disadvantages. First, excess metal is deposited in areas that do not require metal for the functioning of the substrate, i.e., outside the conductor pattern area. Also, the process of sputtering or electroless deposition followed by a bulk metal deposition and selective removal is much more complex and difficult than one time deposition of metal only where its needed. Furthermore, the process is more expensive than the one time deposition of metal.
In one respect, the invention is a material for the manufacture of a multi-layered substrate. The material comprises a dielectric material and a dielectric adhesive coated on one side of the dielectric material. The material also comprises a catalyst layer at the boundary between the dielectric material and the dielectric adhesive. Also, the catalyst layer is thin in comparison to the dielectric material and the dielectric adhesive.
In another respect, the invention is a substrate comprising at least one processed material. Each processed material contains metal pad cavities and vias. Also, each processed material comprises, a first dielectric material, a second dielectric material, and, a catalyst layer. The first dielectric material is above the second dielectric material in a layered arrangement. The processed material according to this invention includes a catalyst layer at a boundary between the first dielectric material and the second dielectric material. Also, the catalyst layer is thin in comparison to the first dielectric material and the second dielectric material.
In another respect, the invention is a method for manufacturing a multi-layered substrate. This method includes the step of forming a first material. The first material is formed by, providing a dielectric material and then providing a layer of catalyst on one side of the dielectric material. Also, a dielectric adhesive is coated on the catalyst layer. According to this invention, the catalyst layer is thin in comparison to the dielectric material and the dielectric adhesive.
In this respect the method for manufacturing a multi-layered substrate optionally includes further steps. The method may include the step of patterning a first internal layer by forming conductor cavities in the first material. The method may also include metallizing the first internal layer, so as to form a pad. A subsequent internal layer on the first internal layer is formed, this done while supporting the bottom side of the first internal layer with a protective temporary release layer. This method may also include the steps of patterning the subsequent internal layer and metallizing the subsequent internal layer. According to this method, additional layers may be formed by repeating the following steps as often as required: the forming of a subsequent layer step; the patterning step; and the metallization step. This method may also include the removing of the temporary release material from the bottom side of the first internal layer, and a further patterning of the bottom side of the first internal layer so as to form a bottom cavity.
In another respect, the method for manufacturing a multi-layered substrate optionally includes further steps. The method may also include the step of providing a first material, as outlined above. The method according to this invention may include further steps. The method may include the step of preparing a starting layer by providing a temporary release layer. This involves laminating the first material to the temporary support. The method may also include the patterning of a first internal layer and metallizing the first internal layer. According to this method, additional layers may be formed by laminating an additional material to the first material. The additional material is substantially similar to the first processed material. This method may also include the repetition of the steps of patterning and metallizing as many times as required, and the step of finishing the temporary support release layer.
In comparison to known prior art, certain embodiments of the invention are capable of achieving certain advantages. One possible advantage is the simplicity of the method for producing a less expensive and electrically superior multi-layered substrate. Another possible advantage is the use of a more desirable dielectric that does not have any catalyst dispersed therein. Additionally, very little of the expensive catalyst is required for the thin layer between the dielectric and adhesive of the raw sheet. Furthermore, the thin layer of catalyst has minimal adverse effects on the electrical properties of the dielectric such as dielectric constant, dielectric loss and bulk resistance. Another possible advantage is that only three types of processes are required for a typical substrate, i.e., ablation, electroless metal deposition, and lamination. Another possible advantage is the stepped via design in combination with the correct dielectric and adhesive layer thickness resulting in reliable electrical connections from layer to layer. These and other advantages will be apparent to those skilled in the art upon reading the following detailed description of preferred embodiments, with reference to the below listed drawings.